Atomic Layer Etch Carves the Path to More Efficient Computing

Atomic layer deposition (ALD) revolutionized semiconductor high volume manufacturing (HVM) in the early 2000s, culminating in the commercialization of 45nm node logic integrated circuits (ICs) with ALD gate stack layers in 2007. IC fabrication is on the verge of another atomic-scale revolution in commercial HVM, but this time the enabling technology will be subtractive instead of additive. Atomic layer etching (ALE) can be used to carefully remove material within complex 3D topographies to create new generations of logic devices, such as horizontal gate all-around (GAA) transistors. ALE will also play a key role in the downscaling of memory devices, making the most of computational advances enabled by GAA integration.

Like ALD, ALE relies on cycling two or more process steps, all of which are ideally self-limiting. A first ALE process step modifies selected surface atoms to change their chemical properties, followed by a chamber purge to remove reaction products and excess reactants. A subsequent ALE process step volatilizes only those modified surface atoms, ideally leaving behind a pristine surface of the original material. Further steps may be added, such as intermediate cleaning steps to remove product residues following the chemical modification and/or volatilization steps.

Research for ALE using plasmas or ion bombardment for the physical removal of surface atoms has been ongoing since the late 1980s. The first HVM tool using plasma ALE entered the market in 2016, with the goal of facilitating dielectric etch beyond the 10nm node.  In contrast, research on ALE using only surface chemical reactions, or thermal ALE, is still in its infancy, with the first publication in 2015.  Both plasma and thermal ALE processes require energy to break bonds in a controlled manner so that only a single layer of surface atoms can be volatilized. In plasma ALE, bonds between the surface atoms and underlying atomic layers are weakened by chemical modification, and these surface atoms are physically removed by ion bombardment. However, the directionality of direct plasma processing limits its use to vertical cuts or recesses.

In thermal ALE, surface atoms are chemically modified to enable volatilization without the need for a physical bombardment step. Instead, the modified surface atoms are chemically volatilized either by abstraction into volatile complexes or by ligand exchange to convert atoms in the solid surface into volatile species. Typical thermal ALE schemes for metals and oxide materials are shown in Figures 1 and 2, respectively. In some thermal ALE schemes, a surface may be converted into an atomic layer of a different material during the ALE cycle; an example is the ALE of SiO₂, which involves the formation of a surface aluminosilicate layer. Since thermal ALE processes involve saturating surface chemical reactions, they can be used to uniformly reduce the thickness of a material in a complex 3D architecture.

While plasma ALE took nearly 30 years to go from early research to HVM implementation, isotropic ALE of metals, dielectrics, and semiconductors are on a faster track. After only a few years of academic R&D, the semiconductor industry has begun to invest engineering resources into making thermal ALE safe, reliable, repeatable, and cost-effective enough to be explored for semiconductor fabrication. ALE precursor chemicals and processes for commercial production on 300mm silicon wafers require:

• Process capability, including (1) an etch per cycle (EPC) which is high enough to enable reasonably fast completion of the ALE process, roughly 1 Å/cycle; (2) selectivity against etching other materials which are exposed on the wafer during process; and (3) minimal damage or residues left behind after the etch.
• Controlling costs to maintain such a process in HVM, including developing, sourcing, and qualifying specialized precursor molecules and operating process tools.
• Environmental, Health, and Safety (EHS) considerations of handling precursor chemistries, process reactions, abatement of etch effluents, and process chamber cleaning.

ALE Applications in IC Fabrication

GAA CMOS logic transistors are now in active R&D by major semiconductor manufacturers and are expected to be in production by 2025. GAA fabrication flows can be considered as extensions of the present state-of-the-art logic device, the fin field-effect transistor (finFET), with the additional need to separate multiple parallel Si channels which are only a few nanometers wide. While there are a few variations of GAA designs, such as nanowires and nanosheets, any horizontal GAA design would benefit from isotropic etching with atomic-scale control to isolate these sensitive channels without damaging them.

GAA channels are grown as epitaxial nanolaminates of Si and SiGe layers. After top-down lithography and etching of this stack into an array of fins, isotropic etching is used to remove the SiGe from fins to leave parallel wires or sheets. Such a process flow depends upon the ability to precisely maintain the shape of the Si layers while removing 100% of the sacrificial SiGe. Wet etch schemes exist for selective removal of SiGe vs. Si, but wet chemistry and chemical residues are extremely difficult to get into and out of an array of nano-wires. Dry ALE processes, in comparison, can be tuned to be faster and cleaner, and can even be done in situ without a vacuum break between the etch and a following deposition step to avoid the formation of native oxide.

As transistors shrink in size, the smallest on-chip metal interconnects in logic ICs must shrink as well. Over multiple metallization steps, several tiers of metal lines are patterned and vertically connected by vias only a few nanometers wide. However, inevitable variations in mask placement, known as edge placement error (EPE), can severely limit the performance and reliability of a device. Fully self-aligned via (FSAV) process flows using ALE have been developed for on-chip metal interconnect processing that minimize EPE by recessing the metal relative to the dielectric using ALE.  Other process flows, such as the Self-Aligned Gate Contact (SAGC) scheme, rely on highly selective “multi-color” etches to make an opening in a dielectric layer only where a metal via should be deposited.

Logic downscaling is not the only driver for ALE development in the semiconductor industry. New integration schemes using ALE can help make memory devices denser and more efficient. Dynamic random access memory (DRAM) can be engineered to use ALE to optimize the shape and composition of charge storage capacitors. Typically, high­-k dielectric materials for DRAM capacitors, such as zirconia (ZrO₂), must be grown to the desired thickness and then crystallized, but physical limitations may make it difficult to completely crystallize a few-nanometer dielectric film with the desired qualities.  Instead, these materials may be deposited as thin amorphous films and then crystallized, followed by an ALE step to precisely thin the dielectric (Figure 3). This method provides the desirable properties of thicker crystallized films while maintaining the higher capacitance of a thinner dielectric.

From Science to Manufacturing Processes

Out of thousands of possible ALE processes to meet the needs of an advanced semiconductor HVM fab, only a rare few will get commercialized to become a “process of record” (POR). Thousands of wafers typically must be processed in rigorous design of experiments (DOE) runs to map out the multi-dimensional process windows of different chemistry sets. Thus, candidate ALE chemistries must show significant promise to meet all of the stringent demands for integration into a process. While this is a daunting task, the physico-chemical principles that can be studied in the lab during the development of ALE reagents and reactions can help identify processes that will be successful in the fab, outlined in the table below.

Bringing thermal ALE from lab to fab

Consideration	Insights from the lab	Needs of the fab
Chemistry	Reactivity with surface Self-limiting surface reactions Precursor vapor pressure	Robustness to process fluctuations Etch isotropy in complex structures Cross-wafer uniformity Wafer-to-wafer reproducibility
Engineering	Etch per cycle Process selectivity Precursor purity Precursor stability Composition of ligands Corrosivity Chemical cost	Throughput Chemical consumption Contamination / residues Device performance Design of reactor Cost of ownership
Environmental	Reaction byproducts Sustainability of chemical production	Environmental impact of process Environmental impact of precursor production Effluent abatement

Repeatability in a process is fundamental for manufacturing control. An ideal atomic layer process is inherently robust against fluctuations in process variables: when each chemical reaction is limited to the surface, the process proceeds one atomic layer at a time. For example, consider the classic ALD process using trimethylaluminum (TMA) and water (H₂O) to form alumina (Al₂O₃): since the reactions of TMA chemisorption and ligand exchange with H₂O are readily self-limiting under a wide range of conditions, the process gives consistent results on most ALD reactors.

The need for self-limiting surface reactions raises a significant challenge for the surface modification step in an ALE process. For example, ALE processes for dielectric oxides such as Al₂O₃, ZrO₂, or HfO₂ typically require a fluorination step to convert the surface layer into a metal fluoride which can be volatilized in a subsequent ALE step. However, fluorination may not be limited to the surface atomic layer. Different fluorinating agents can yield different EPC values for otherwise identical processes, and EPC is higher for amorphous vs. crystalline materials with otherwise identical composition, suggesting that the defectivity of the material may promote diffusion of the fluorinator.

As shown schematically in Figure 4, poor control of a surface modification chemistry presents challenges for isotropic ALE in complex nano-architectures such as deep trenches. The material near the top of a trench may experience a higher EPC if the reaction is poorly controlled, since it will receive a greater dose during the reactant pulse than the material deeper in the trench. Additionally, diffusion of residual halogens or other contaminants from the ALE precursor into the film can have a detrimental effect on the properties of the materials they etch, such as increased current leakage through dielectric films.

Safe, Sustainable, and Efficient ALE

New processes for semiconductor manufacturing must be developed with safety and sustainability in mind from the start. A process developed in the lab may show a clean EPC with excellent selectivity, but it may be forbidden in the fab if it uses unsafe or unsustainable chemistries. For example, many halogenating agents used in ALE studies present a risk to corroding common metals, even stainless steel. Reaction byproducts and potential issues such as condensation of vapors in pumps or pump lines must also be considered.

From an environmental perspective, many halogen-containing compounds are extreme greenhouse gases with effects on global warming exceeding those of CO₂ by orders of magnitude. Even small quantities of greenhouse gases generated per ALE cycle will add up in a global semiconductor industry that processes millions of wafers per month. Care should be taken in selecting ALE processes for which halogenated effluents can be mitigated.

On the other hand, ALE can improve the sustainability of semiconductor manufacturing by potentially replacing wet cleans with “dry” processes inside vacuum chambers. Precise cleaning steps and specialty surface preparations may use similar chemical treatments as ALE process steps, improving device yields while reducing fab effluents. Targeting ALE process development to replace wet cleans could dramatically reduce the use of acids and per- and polyfluoroalkyl substances (PFAS), a key challenge in the semiconductor industry.

ALE is poised to become an integral part of semiconductor HVM, but technical challenges remain for ALE to meet the promise of highly selective, layer-by-layer removal of a specified material. As we fill out the library of ALE processes, we need to keep in mind the challenges of ALE integration to ensure that a process can be scaled up in the semiconductor fab. The atomic layer processing community must focus on developing candidate chemistries which can meet the rigorous demands of HVM, and keep an eye out for other opportunities by which ALE can replace traditional methods, such as wet etch, with a sustainable alternative.

This is a blog post initiated by our sponsor Intermolecular, a subsidiary of Merck KGaA, Darmstadt, Germany

References:

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