Adrie Mackus, Marc Merkx
Recently, the 4th Area Selective Deposition workshop (ASD2019) took place at IMEC in Leuven, Belgium. During this workshop it became clear that the main application the semiconductor industry is currently looking at for area-selective atomic layer deposition (ALD), is the fabrication of fully self-aligned vias (FSAV) in the back end of line (BEOL). FSAV (also referred to as fully aligned via, FAV) can be considered as an extension of the self-aligned via scheme (SAV, described in Ref. 1), which has been employed since the 32 nm node. The use of area-selective ALD to enable FSAV fabrication was highlighted in almost all of the presentations given by companies in the semiconductor industry and by IMEC,2–6 and received by far the most attention among the envisioned applications that were discussed. The FSAV application has the potential to become an enabler for the implementation of area-selective ALD in semiconductor processing, similar to the role high-k dielectrics have played for ALD. Once ALD was implemented in the semiconductor industry for the high-k gate oxide from the 45 nm node on, it was also considered for many other layers in subsequent nodes.7 Possibly, a similar development can be expected for area-selective ALD.
Although area-selective deposition is currently in production for capping of Cu with Co, ALD processes have yet to be implemented for selective processing in high volume manufacturing. Consequently, there are still several open questions regarding what is needed to allow for the implementation of area-selective ALD in the semiconductor industry: (i) What are the most relevant materials for which to develop area-selective ALD processes? (ii) What is the target thickness that should be aimed for? (iii) What materials should be considered as starting surfaces? (iv) How much deposition is acceptable on the non-growth area? The answers to these questions strongly depend on the eventual application, meaning that it is currently unclear what we are heading for. For the ASD community, it might be good to initially focus on a specific application in order to reach consensus on what should be taken into account during area-selective ALD process development. Now that the FSAV application is attracting most attention, we might consider this application as a sort of model system for addressing these questions. This blog post is an attempt to trigger more discussion on what is relevant for the use of area-selective ALD in high volume manufacturing. With this effort we hope to contribute towards aligning ongoing research activities in area-selective deposition.
Figure 1. (a) Edge placement error (EPE) in interconnect fabrication. Due to the reduced spacing to the neighboring line, shorts can occur. (b) FSAV scheme based on recess etching. (c) FSAV scheme based on area-selective ALD.
Motivation: edge placement error (EPE) in interconnect fabrication
The challenge in lithography for BEOL processing is not only in patterning small structures, but alignment of metal vias and metal lines with respect to each other is also becoming more and more difficult. As illustrated in Figure 1a, the desired case would be that a via is patterned exactly at the right spot on a metal line below. In practice, however, there is typically an edge placement error (EPE), which is defined as the distance between the intended and the actual position of the feature edge. An EPE of ~ 2 nm can be expected, based on the 2.0 nm overlay accuracy of EUV lithography.8 This value is relatively large considering typical via and line widths in the order of 10-15 nm and pitches of < 30 nm. An EPE in a fabricated via has several consequences on performance, reliability and durability of the device. If the via is located too close to the next metal line, over time shorts can develop (driven by the electric field), which is often described using the term time-dependent dielectric breakdown (TDDB). In addition, proximity to a neighboring metal line leads to a higher capacitance between the via and the metal line. The EPE also reduces the contact area between those metals, thereby increasing the contact resistance. A higher capacitance and a higher resistance together give an increased RC-delay, i.e. the time required for transistor/device switching. Furthermore, a reduced contact area lowers the electromigration (EM) reliability, which can also lead to eventual failure of the device. These consequences of EPE in interconnect fabrication are currently limiting the downscaling of semiconductor devices.
The illustrations in Figure 2 show more details of the conventional process flow, which reveal an additional issue. First, a multilayer dielectric cap is deposited uniformly on metal layer Mx, typically using ALD processes. This multilayer cap acts as diffusion barrier for the Cu from the underlying metal lines and as etch-stop layer in subsequent processing steps. Next, the interlayer dielectric (ILD) of layer Mx+1 is deposited, patterned, and etched (with the multilayer cap acting as etch-stop layer), resulting in the structure shown in Figure 2a. Because the multilayer cap consists of dielectric materials, it needs to be partly removed before depositing the metal of Mx+1 in order to ensure electrical contact between the via and the Mx metal line. This is referred to as via-open or punch-through and is depicted in Figure 2b. The etching step for the via-open is performed using an anisotropic etch process. In case there is an EPE, the ILD of the Mx layer is also partly etched during this step. Subsequently, metal is deposited in the voids of the ILD region, leading to a so-called tiger tooth defect (Figure 2c).9 This defect exacerbates the aforementioned consequences of EPE, since the proximity to neighboring metal lines is increased even further.
Figure 2. Conventional process flow for via patterning, illustrating that an EPE can also result in a tiger tooth defect.
FSAV scheme based on recess etching
A solution to these limitations is to create topography, for example by performing a recess etch.10–12 As illustrated in Figure 1b, even if the via is patterned at exactly the same place (with an EPE of ~2 nm), a recess etch results in an additional spacing between the fabricated via and the neighboring metal line. The increased spacing improves the device reliability and mitigates the RC-delay. In addition, the FSAV scheme allows for patterning vias with a larger critical dimension (CD) as illustrated in Figure 3.10 Scaling to a larger CD guarantees maximum contact area, which is beneficial in terms of electromigration reliability and contact resistance.
Figure 3. Merits of creating topography by either recess etching or area-selective ALD.
The FSAV scheme based on recess etching requires an etching process to create the topography. Etching of Cu is however known to be challenging (which is why the damascene scheme has been developed in the first place). IMEC considered a recess etch based on oxidation of the metal using H2O2 solution, followed by CuOx etching using HF-containing solution.11 Note that the barrier (e.g. TaN) and liner (Ta) also need to be etched.
In addition, several other challenges have been identified for the FSAV scheme based on recess etching. It is difficult to control the thickness of how much material is etched using wet chemical etching. Moreover, the metal grains and the grain boundaries etch with different rates, which leads to a relatively rough surface. Finally, tiger tooth defects are not prevented, but their effect is only mitigated by creating the topography. These challenges motivate the exploration of alternative FSAV schemes based on area-selective ALD.
FSAV scheme based on area-selective ALD
Area-selective ALD can be employed to selectively deposit a barrier layer on the ILD as shown in Figure 1c.9,13 This creates a topography equivalent to the one obtained by using recess etching, but with a better control over the barrier thickness and without roughening the metal. Moreover, area-selective ALD allows for deposition of a dielectric barrier consisting of a different material than the carbon-doped oxide (CDO) used as ILD, which is potentially beneficial to prevent the formation of tiger tooth defects as discussed in more detail below.
In general, area-selective ALD exploits differences in surface chemistry in order to deposit material at specific regions on a substrate.14–16 For this application, an area-selective ALD process is needed that leads to deposition on the ILD (i.e. CDO) as the growth area, without coating the metal non-growth area, such that a similar topography as obtained by the recess etch is created. In other words, an area-selective ALD process for dielectric-on-dielectric with a metal as non-growth area is required.
With interconnect technology going through a transition period,17,18 which metal to consider as non-growth area is currently up for debate. First of all, the question is whether we need to consider Cu, Co, W or maybe even Ru in the future. While Intel and TSMC are currently implementing Co for the bottom metal layers,19 it remains a question whether the rest of the semiconductor industry will follow suit and whether we only need to consider the bottom layers. However, even when targeting Cu as the main material, we still might want to focus our attention to blocking the ALD growth on either Co or Ru, when considering that Cu is typically capped with these materials to improve the electromigration reliability. There is currently no consensus whether it is better to apply area-selective ALD before or after capping. If you first perform area-selective ALD, it is likely that the material mushrooms over the diffusion barrier (i.e. lateral broadening due to the isotropic nature of ALD growth), with the risk that subsequent capping might not entirely encapsulate the Cu. Consequently, it appears to be preferred to first perform the metal capping, which means that Co or Ru needs to be considered as non-growth area, instead of Cu.
The deposition method of the metal and what is left on its surface after deposition should also be considered, because the exact state of the surface can greatly influence an area-selective ALD process. For example, when using a self-assembled monolayer (SAM) to block the ALD growth, residues on the non-growth area can hamper the formation of an ordered monolayer. Several deposition techniques are employed in semiconductor fabrication to prepare metals, including electroplating and chemical vapor deposition (CVD). These methods produce a metal with impurities on its surface (e.g. carbon from the CVD process, inorganics from electroplating baths). Chemical mechanical polishing potentially leads to metal impurities (e.g. Ta or Cu) or residues (e.g. anti-corrosive additives like benzotriazole20) on both the dielectric and metal surfaces. Furthermore, the cleaning procedure employed, and whether the metal surface is oxidized should also be taken into account. The discussion of what materials to consider as non-growth area becomes even more complex when we also consider that no deposition should occur on the barrier and liner materials.
Material choice and requirements for area-selective ALD
As mentioned before, one advantage of area-selective ALD over a recess etch is that the barrier layer can be a different material than what is used for the ILD. Preferably, the area-selective ALD process allows for deposition of a low-k material to minimize its influence on RC-delay. The target for the dielectric constant is that it should be below 6, and preferably even lower. Moreover, the barrier material should be resistant to the etch chemistry of via-open step to prevent the formation of tiger tooth defects. Lastly, the deposited material should be of high dielectric quality (both intrinsic as well as extrinsic) in order to have good TDDB reliability. Lower dielectric quality results in a larger leakage current during operation which can significantly decrease the mean time to failure (MTTF) of the dielectric barrier layer.21
There are unfortunately no materials that have a low-k value and are at the same time sufficiently resistant to the etching chemistry of the via-open step. As an alternative scheme, a stack of a low-k material and an etch-stop layer can be deposited as illustrated in Figure 4. Note that this still requires the application of the multilayer dielectric cap of Figure 2 after performing the two area-selective ALD processes. This new etch-stop layer protects the low-k barrier from being etched during the via-open step (when the previously-mentioned etch-stop layer is removed), which decreases the chance that a tiger tooth defect occurs.
Figure 4. Alternative FSAV scheme resulting in a stack of low-k material and an etch-stop layer.
For FSAV schemes based on recess etching the target thickness of the dielectric barrier is approximately 10 nm.11 When using area-selective ALD, the thickness requirement is dependent on whether the dielectric barrier also functions as an etch-stop. If area-selective ALD is only employed to create a topography, a thickness of 10 nm can also be defined as the target. In case the dielectric barrier is resistant to the via-open etch chemistry (thereby preventing the formation of tiger tooth defects), a barrier of less than 5 nm is sufficient.
An important aspect to discuss further is how well the area-selective ALD process(es) should perform in terms of selectivity. Any deposition of dielectric on the metal surface is undesired since it increases contact resistance. As a target selectivity, a value of 100:1 has been mentioned. In practice it will be extremely difficult to meet this requirement, especially when also considering the presence of impurities and residues from earlier processing steps. The main question is how much nuclei of dielectric material influence the RC delay. This is dependent on the material that is deposited using area-selective ALD, and on the size/distribution of the nuclei on the metal. Especially the formation of so-called killer defects should avoided, i.e. a region where for example area-selective ALD of dielectric material did not occur, because such defects can potentially lead to failure of the entire chip. At this stage, the metrology for measuring the selectivity and for detecting killer defects has not been established yet, which also requires further attention.
Current status of area-selective ALD for FSAV
What are the options based on currently available area-selective ALD processes? Dielectric-on-dielectric deposition with metal as the non-growth area has been reported in the literature for ZnO, TiO2, HfO2, ZrO2, Hf3N4 and Al2O3 ALD.22–27 Most of these materials are not suitable for this application because they have k values surpassing the target maximum value of 6. At ASD2019, IMEC reported on area-selective ALD of HfNx (k = 6.4) using vapor-phase dosing of n-undecanethiol (UDT) molecules.28 Instead of an ordered SAM, a multilayer UDT masking layer was obtained of 3-8 nm in thickness. Their results nicely illustrated the influence of the surface preparation on the selectivity. UDT molecules on Cu cleaned using a forming gas treatment could block the ALD growth for 50 ALD cycles, while blocking for at least 500 cycles was observed for Cu after CMP. On patterned wafers, deposition of a barrier of 11 nm HfNx was demonstrated. A high line edge roughness (LER) was observed, which was explained by undesired passivation at the edge of the SiO2 growth area. This effect could be reduced by performing a forming gas treatment after SAM functionalization.
Area-selective ALD processes of Al2O3 (k = ~9) are also interesting for this application because Al2O3 can act as an etch-stop layer during the via-open step (and can for example be used in the scheme of Figure 4). However, area-selective ALD of Al2O3 is known to be challenging, due to high reactivity of the trimethylaluminum (TMA) precursor.29 A collaboration between KU Leuven, IMEC, and ASM presented results at ASD2019 on area-selective of Al2O3 on SiO2 involving Cu functionalization using 1-octadecanethiol SAMs.30 Although it was not discussed, it likely that a precursor different from TMA was used. Also in this study there was attention for the preparation of the substrate, and it was found that rinsing the Cu with ethanol resulted in a pinhole-free SAM. On patterned samples, loss of selectivity was observed after depositing 6 nm of Al2O3. This could be improved by performing post-deposition cleaning using acetic acid. Cross-section TEM revealed that the Al2O3 is not blocked on the Ru/TaN barrier layers.
Our SiO2 area-selective ALD process, developed in collaboration with Lam Research, received some attention for this application because of the low-k value of SiO2 (k = ~4). Area-selective ALD was obtained by dosing acetylacetone (Hacac) inhibitor molecules in vapor-phase using ABC-type cycles.31 So far, we have reported results for Al2O3, TiO2, or HfO2 non-growth areas,31 but more recently we demonstrated that the growth can also be blocked on Co. The current status is that a SiO2 layer of ~1.5 nm can be deposited selectively when blocking Co (and ~2.5 nm when blocking Al2O3),32 which does not meet the target thickness yet. Our contribution at ASD2019 focused on the mechanisms of precursor blocking, which revealed important insights for improving the selectivity in the future.33
Since most of the current area-selective ALD processes do not come close to the required selectivity, selective etching as a correction step will need to be considered. Depending on the impurity level, such a correction step could be implemented either during ALD using a supercycle recipe or as a post-deposition etch back.16
It should be noted that these are the results reported by academic research groups. It can be expected that at this stage also many experiments have been conducted within the semiconductor industry specifically targeting this application. From the fact that all the main players are talking about the FSAV application, it can be concluded that there currently is a real need for developing FSAV schemes based on area-selective ALD. Hopefully, this application will indeed serve as a stepping stone for the maturing of area-selective ALD technology.
This blog is based on our personal understanding of FSAV fabrication schemes on the basis of limited literature (Refs. 10,11) and discussions with researchers and engineers from various companies in the semiconductor industry. For sure some details are missing or oversimplified. If you have comments or suggestions for getting to a more complete picture, please leave a comment below (or contact us in a private communication). Based on the comments we will update this blog, or post a refined description.
We would like thank the presenters at ASD2019 for sharing details on the application possibilities of area-selective deposition, and acknowledge Dennis Hausmann (Lam Research) and Robert Clark (TEL) for fruitful discussions.
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