Metal-on-metal area-selective deposition-Why cobalt succeeded where tungsten failed

Please cite as
M.J.M. Merkx, A.J.M. Mackus, Metal on metal area-selective deposition: Why cobalt succeeded where tungsten failed. 2022, 1. AtomicLimits.

Cover image was reprinted from ref 2, with permission from Elsevier.

In 2019 we wrote a blog post on the use of area-selective deposition (ASD) for the fabrication of Fully Self-Aligned Via (FSAV) structures and how this application could enable further downscaling in the semiconductor industry. Our evaluation of the FSAV application showed that there is great potential for the implementation of ASD to mitigate or even eliminate challenges regarding alignment and reliability of device structures. In this blog post, we evaluate a more mature application of ASD which has already been adopted by industry: metal capping of Cu interconnects. These posts are part of a series of ASD applications that we want to evaluate and where we focus on exploring applications in the back-end-of-line of semiconductor device fabrication. The purpose of this series is to highlight promising ASD applications that require different forms of substrate selectivity (e.g. dielectric on dielectric deposition for the FSAV, metal on metal deposition for selective metal capping, etc.). In addition we attempt to shed light on the requirements of these applications in terms of selectivity and material choice/quality.

Currently, ASD is in production in high volume manufacturing for Co capping of Cu interconnects. Interestingly, it was also attempted to implement ASD several decades ago for back-end-of-line (BEOL) gapfill using chemical vapor deposition (CVD) of W. However, W ASD has not been successfully adopted by industry due to a too high defectivity and insufficient yield (i.e. percentage of functional chips on a wafer).¹ After failing to implement ASD of W for several decades, the industry has been hesitant to attempt the implementation of new area-selective deposition (ASD) processes. This raises the question why ASD of Co has managed to make it to the application whereas ASD of W failed: is area-selective CVD of Co simply more easily achieved, or have the requirements for ASD applications changed in the meantime? Here, we compare the attempt to integrate area-selective CVD of W in high volume manufacturing to the recent success with area-selective CVD of Co, and try to learn from that analysis what is required to successfully introduce an ASD process in the semiconductor industry

Figure 1: In general, metals are difficult to etch and therefore difficult to pattern. For this reason, the industry has been using bottom-up (i.e. non-subtractive) approaches for BEOL metallization for the last two decades.³ However, the currently used approaches are quite complex, relying on (a) a blanket deposition, chemical mechanical polishing (CMP), and post-fabrication cleaning steps to make the desired structure. Using this approach, it is a challenge to avoid the formation of voids in the interconnect structure, while the CMP step leaves metal residue on the dielectric surface, requiring post-fabrication cleaning steps. (b) By selective deposition of the metal, no voids can form in the deposited metal and no CMP step is required to obtain the desired structure.

History of W ASD for metal gapfill

Via metallization using a blanket deposition can lead to defects in the interconnect structure in several different ways, as shown in Figure 1. Although a large part of these defects can be avoided by process/reactor optimization and post-fabrication cleaning steps, a simpler solution is to deposit the metal selectively on the metal surfaces where it is desired (metal-on-metal or MoM selectivity), as shown in Figure 1b. To this end, area-selective CVD of W using WF₆ and H₂ gas has been studied since the 1980s.^4–8 Both precursors contribute to the selectivity of this process: (i) the WF₆ selectively adsorbs on metals and on Si, but not on SiO₂ and (ii) the H₂ gas selectively dissociates on metal surfaces to deposit W. Even after extensive research, area-selective CVD of W could not achieve the required selectivity for the application. The loss of selectivity was found to be have two main causes; (i) pre-existing impurities on the non-growth area and (ii) intermediate reaction products formed during precursor adsorption on the growth area that can end up on the non-growth area, see Figure 2. Careful cleaning and preprocessing steps have been shown to decrease impurity levels and therefore improve the selectivity,⁹ however the formation of intermediate products is more difficult to prevent.

It has been shown that, during the adsorption of WF₆ and H₂ on the metal growth area, WF_x and HF are formed which can re-volatilize into the gas phase.⁷ As shown in Figure 2, these WF_x species can adsorb on the non-growth area, resulting in undesired nucleation of W. In addition, the HF forms SiF_y species on the SiO₂ surface which act as nucleation sites, or can even etch material where it is not desired. Overall, these intermediate products cause area-selective CVD of W to have a lower selectivity on patterned substrates as compared to depositions on blanket substrates. Another concern is that the underlying metal line needs to be exposed for ASD of W to be viable as shown in Figure 1. In case the metal via requires a liner or diffusion barrier, both the sidewall and underlying metal will typically be covered with the liner and/or diffusion barrier and therefore the ability to achieve ASD is lost.

Figure 2: Schematic illustration showing the selectivity loss mechanisms for area-selective W CVD on patterned substrates. Intermediate WF_x adsorption products can re-volatize and re-adsorb on the SiO₂ non-growth area. In addition, HF is formed as reaction product during W CVD which can fluorinate and etch the SiO₂, the formed SiF species act as nucleation sites for WF₆ adsorption.

Recent developments in ASD of Co for metal capping

Because of downscaling, the surface area of metal interconnects has increased relative to their volume, which decreases the reliability of metal wiring because of electromigration (EM), see Figure 3. The main purpose of metal capping is to bind the Cu at the surface more strongly, i.e. the layer acts as a sort of glue to keep to Cu in place. By doing so, the Cu becomes more resistant to EM. Co, Ru, Mn, and W capping layers have been reported to be interesting materials for improving the EM reliability of Cu interconnects.^10–13 For metal capping layers it is important that the material has: (i) a good adhesion to the Cu wiring, (ii) low line resistance, and (iii) a high EM activation energy. For now, Co seems to be the material of choice for metal capping, ^{10, 13} although Ru appears to be another promising candidate.¹⁴ In addition to pure Co, Co-based alloys like CoW_xP_y have been reported to improve Cu interconnect reliability even further.¹⁵ By tweaking the values of x and y in these alloys, a higher EM activation energy can be achieved while maintaining a low line resistance.

Figure 3: Schematic illustration showing the forces that act on the Cu atoms in the metal lines when a current is passed through the interconnect. Depending on the strength of these forces and on the bonding of the Cu, electromigration can take place, resulting in voids or extrusions.

ASD of Co has been achieved using electroless Co deposition and area-selective CVD. Especially area-selective CVD is of interest as it can be applied in vapor-phase, while it is also less complex to control the deposition as compared to electroless deposition. In addition, CVD films are typically higher quality (i.e. higher density, fewer voids). As shown in Figure 4, when capping Cu interconnects with a thin Co film, it is vital that the deposition of Co on the dielectric material between Cu lines is kept to a minimum. In that respect, ASD of Co for metal capping suffers from similar limitations as was previously encountered for ASD of W. Any loss of selectivity results in a decreased yield and an increased leakage current or even shorts. After CMP of the Cu lines, typically 10¹¹ – 10¹²atoms/cm²metal defects remain on the dielectric surface.¹⁶ Although the number of these metal defects can be reduced using post-CMP cleaning steps, some of these defects will persist on the dielectric non-growth area. Even if the Co ASD process that is employed has perfect metal/dielectric selectivity, Co nucleation will still take place during ASD on these metal defects. When applying area-selective CVD of Co on Cu interconnect structures, it has been reported that the yield and leakage current degrade for thick (>3 nm) Co capping layers, which is attributed to loss of selectivity.^{17, 18} Improved EM reliability can fortunately already be achieved for Co capping layers as thin as 1.6 nm.^18–20 Instead of having a minimum Co thickness, it is likely more important for the Co to form a closed layer that completely covers all of the exposed Cu surface.

Figure 4: Electromigration reliability of Cu wiring can be improved by capping the Cu surface using a thin Co film. To prevent an increase in leakage current and a decrease in yield, metal defects on the low-κ dielectric, caused by the ASD process, should be kept to a minimum.

Mushrooming (i.e. lateral growth) is another concern that typically restricts the adoption of ASD processes in the industry. In the case of selective metal capping, mushrooming is also undesired because it leads to Co growth over the dielectric in between Cu lines, and therefore leads to an increase in RC-delay and a higher risk of shorts. Especially considering that the spacing between interconnect wiring is currently in the order of 10 nm, even a little mushrooming can lead to issues. Fortunately, Cu lines are typically slightly recessed with respect to the surrounding dielectric after CMP because of corrosion and so-called dishing effects.²¹ Such a recess is typically undesired, however, for ASD it provides a way to mitigate mushrooming, as shown in Figure 5. Patents by Global Foundries, IBM, and Samsung even report a separate metal recessing step as pretreatment for their selective metal capping processes.^22–24 Currently, deposition within a confined structure is the only reported solution to fully prevent mushrooming for ASD.²⁵ However, as shown in Figure 5, mushrooming is only confined as long as the Co thickness does not exceed in the recessed area. The fact that mushrooming does not play a large role in this application likely contributed to the implementation of Co ASD in industry.

Figure 5: Illustration showing how Co mushrooming is prevented by the Cu recess introduced by the CMP step. Lateral growth is mitigated as long as the Co thickness does not exceed the depth of the recess.

Current status area-selective CVD for metal capping

Several area-selective CVD processes have been reported that could satisfy the requirements for ASD for metal capping. Area selective CVD processes for Co, Ru, Mn, and W have been reported that are all capable of several nanometers of selective deposition with good selectivity.^{4–8, 11, 26, 27} For cobalt specifically, area selective CVD processes has been reported using Co precursors Co₂(CO)₈,²⁸ Co₂(CO)₆(C₆H₁₀),²⁰ CoCp(CO)₂¹²as the precursor. Several strategies to obtain a higher selectivity have also been explored in the literature. For example, Ryu et al. found that the CoCp(CO)₂precursor has a higher kinetic barrier for adsorption as compared to Co₂(CO)₈¹²whereas Zhang et al. employed co-dosing of an NH₃ inhibitor during deposition to improve the selective growth behavior of Co₂(CO)₈.²⁸ Interestingly, both processes can achieve several nanometers of Co deposition without observable deposition on the SiO₂ non-growth area. However, as mentioned before, studies that applied similar area-selective CVD processes on Cu interconnect structures report significant loss of selectivity above 3 nm of Co deposition.^{17, 18} This raises the question what causes the observed degradation of interconnect performance when applying area-selective Co CVD to device structures, whereas the reported selectivity for blanket studies is much better. Similarly to what was observed for ASD of W, CMP defects could play a large role in CVD nucleation on the non-growth area. In addition, the discrepancy reported for process selectivity on device structures as compared to blanket studies could also be related to mushrooming of the growing Co film, see Figure 5.

Why was ASD of Co but not ASD of W adopted by industry?

The answer to the question why ASD of Co is now adopted by industry, whereas ASD of W was not, contains several elements. Firstly, Co ASD for metal capping only requires a few nanometers of deposition on the growth area, whereas current gapfill application require 10s of nanometers of selective deposition. The much smaller target thickness for metal capping as compared to metal gapfill is more easily achieved using ASD. Considering most state-of-the-art ASD processes start to lose selectivity after several nanometers of deposition, ASD is likely most suited for target thicknesses below 10 nm.²⁹ Secondly, the mechanisms that cause a loss of selectivity for area-selective CVD of W show that the selectivity obtained in academic studies not always translates to ASD on device structures. If ASD requires extensive cleaning steps and very specific process conditions to be viable in semiconductor fabrication schemes, it might no longer provide the process simplification for which it is being considered. Lastly, in case a liner or barrier material is required, the capability to do ASD is lost unless the liner/barrier is also deposited selectively. One thing to keep in mind is that every new fabrication processing scheme always competes with process optimization of existing fabrication schemes. If an ASD process does not significantly outperform the existing fabrication schemes it will likely not be adopted by industry.

It should be noted that in the 1980s, when area-selective CVD of W first attracted interest in industry, microchip technology had only just surpassed the 1 µm technology node. As a result, area-selective CVD of W was required to deposit in the order of 100 nm – 1 µm of material selectively, which is obviously more challenging than a few nanometers of selective deposition. This means that, for future technology nodes, ASD for metal gapfill could potentially be interesting when the application requires a lower target thickness. The tool manufacturer Applied Materials is currently selling a dedicated tool for area-selective CVD of W for metal gapfill,³⁰ indicating there is some interest again to retry the adoption of ASD of W. Given that Intel and TMSC are currently also implementing Co interconnects for the bottom metal layers,³¹ instead of Co-capped Cu, area-selective CVD of Co for metal gapfill is likely being considered by industry as well. Especially because ASD of Co is already in use for metal capping, there should be enough incentive for industry to attempt ASD of Co for metal gapfill.

The content of this blog is based on what is known in literature and discussions with researchers and engineers from various companies in the semiconductor industry. This blog likely does not describe the full story. Please leave a comment or contact us privately if you have any comments or suggestions to supplement this story. Based on the feedback we will update this blog or post a refined description.

Acknowledgements:

We would like to thank Dennis Hausmann (Lam Research) and Robert Clark (TEL) for the interesting discussions.

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