Two weeks ago I attended the SPIE Advanced Lithography conference in San Jose (February 26 – March 2) and I got so much inspired that I wanted to write a blog about it. It was my second time at this conference as I decided to come back after attending last year when I was asked to give an invited presentation about “Atomic layer processing for nanopatterning”. The SPIE conference is not so much known for its presentations about groundbreaking science. As a matter of fact the majority of attendees come from industry (with a very significant fraction of ASML people!), but I like the conference for other reasons. The main one being the fact that one gets a completely different, and probably much better, insight into what’s really happening at the forefront of the semiconductor industry. And it is not so much the lithography itself I’m interested in, it is the fact that “lithography has become patterning”. The latter means that the so-called “semiconductor scaling” is not just a matter of realizing a better optical resolution anymore. We all know that we are stuck at 193-immersion already for several technology nodes (industry started to use it for the 65 nm technology node, currently 10 nm is being implemented in industry) while we are still waiting for EUV (13.5 nm) to become available for high-volume manufacturing. Since several years, the so-called “scaling” – which is currently a misnomer anyway – is enabled by innovations in 3D material processing. The latter is the reason that I really got interested, most particularly as the scaling is currently heavily depending on my favorite thin film deposition technique: atomic layer deposition or ALD!
The advancement in technology nodes is currently enabled by so-called method of self-aligned multiple pattering, abbreviated as SAxP. ALD is a real key technology within SAxP and therefore this is where this blog will be mainly about. Note that this blog also covers some things presented last year at the SPIE conference. But after a year digesting the newly gained knowledge and after reading some conference proceedings, I think I can do a much better job in giving a (hopefully) fairly accurate, updated overview.
Well, let’s first go back a few years before addressing the current state of the art. My interest in this kind of patterning got triggered in 2010 when I read a paper of Beynet et al. from ASM . They described how ALD on photoresist lines could be used for so-called pitch splitting. They called it spacer-defined double patterning (SDDP) and soon, after digging into this topic, I learned that this method was extremely important in semiconductor industry. At that time, the approach was considered especially important for memory applications, which is very much cost-driven and which requires patterning of repeating structures. The method involved plasma ALD of SiO2 with the plasma being very important as the deposition on top of photoresist clearly required low temperature processes. Therefore we also included a description of the method in our review paper about plasma ALD. Yet at that time, the importance of this method was not well-recognized. Not by me but also not by the ALD community. For this community, the method came basically out of the blue: suddenly there was a new application of ALD in the semiconductor industry while we had not heard about it during any ALD conference.
In 2011, we also started to do some work on it ourselves. We had been pushing low temperature ALD already for some time and in the MSc student Robin Roelofs (now at ASM) we found a person that could do some nice work on it. We learned a lot from his experiments but due to our limited experience with lithography as well as our limited advanced litho capabilities, we were not too impressed by our results ourselves (see the example below). So we decided not to report on it. On the other hand, if I look at some figures that were presented during the SPIE conference, I realize that we might not be doing that extremely bad at the time. The work was certainly a driver to invest even more in low temperature ALD and our paper about room-temperature ALD of SiO2, Al2O3 and TiO2 was an indirect result of it. As will become clear below, this work might have been important for the SAxP development by industry in the recent years. By the way, our interest in ALD for nanopatterning has also become apparent by our review paper about nanopatterning that appeared in 2014 (“The use of atomic layer deposition in advanced nanopatterning”). This paper addressed both self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP).
Spacers resulting after spacer etch for the SADP case in which the Al2O3 spacer was directly deposited on PMMA resist. The spacers were etched by ion milling and the PMMA was removed by acetone. The spacers show severe “leaning”. (MSc thesis Robin Roelofs, TU/e).
Let’s now go back to the SPIE lithography conference and focus on the reports on SAxP processes, more particular on SAQP as that is the hot topic – also for logic – at the moment. The SAQP processes come in many flavors. The first process is the one for etching finFETs reported by imec last year as well as this year. As explained by Efraín Altamirano-Sánchez and colleagues, this process employs two hard mandrels (also called cores) and spacers of SiO2 prepared by plasma ALD. With this they are able to reach a 22.5 nm pitch between the finFETs which meets the specs for 7 nm and 5 nm node devices. Note that the mandrel-1 is amorphous carbon (a-C) and mandrel-2 is amorphous silicon (a-Si). These sacrificial materials are prepared by PECVD.
SAQP process with two hard mandrels as reported by imec. The first hard mandrel is a-C and the second hard mandrel is a-Si. Both spacers are SiO2 prepared by plasma-enhanced ALD.
TEL on the other hand reported last year an SAQP process that differed from the two hard mandrel scheme typically reported. Angélique Raley and Sophie Thibaut and co-workers reported a spacer-on-spacer SAQP scheme which requires less process steps. In this scheme, the first spacer forms the core for the second spacer. The first spacer is either deposited on the photoresist lines (see also the SDDP process reported by Beynet et al.) or on an organic mandrel. The first spacer is ALD SiO2 and the second spacer ALD TiO2.
SAQP process employing spacer-on-spacer scheme as reported by TEL. The first mandrel is the organic film from the litho stack with on top the Si ARC.
This year it was disclosed that the drawback of this process was that a plasma-free etch was required for Si ARC removal (Si ARC is a silicon-based bottom antireflection coating to reduce the negative effects frominterference of the litho radiation) as well as a plasma treatment of the mandrel to avoid spacer leaning (which leads to enhanced edge placement errors). Therefore, Sophie Thibaut of TEL presented an alternative process in which an additional hard mandrel was used. This would go at the expense of adding one extra layer (a-Si mandrel) but the advantage that it only involves all-dry processes which can take place within one chamber. Replying on my question, I learned that the first spacer is SiNx and the second spacer is TiO2 in this case.
Modified SAQP process employing spacer-on-spacer scheme with additional hard mandrel as reported by TEL. The hard mandrel is an a-Si mandrel.
I find these SAQP processes very interesting and there are a couple of things I took away from the presentations. First of all, it is interesting that mandrels are typically a-Si and a-C prepared by PECVD. As a MSc and PhD student I worked on the deposition of these materials by plasmas! The other interesting thing is that currently several spacer materials are being used, likely all prepared by plasma ALD. In addition to SiO2, we now also have TiO2 and SiNx and potentially also other materials. I’m quite sure that people have tried Al2O3 and I have also heard rumors of a company even using HfO2. This also shows that our work on low temperature ALD of materials other than SiO2 has been quite relevant. By the way, the importance of using plasma ALD instead of thermal ALD was also nicely outlined by TEL last year. Plasma ALD TiO2 (at 150 ⁰C) led to a smaller roughness than thermal ALD TiO2 (at 250 ⁰C). Also their spatial ALD NT333™ tool looks very interesting! See the figures below.
TiO2 spacers deposited by thermal ALD at 250 ⁰C and plasma ALD at 150 ⁰C (source)
Schematic of chamber of TEL NT333™ tool. Six wafers spin around the center of the chamber and go through four different sections for precursor (TiCl4) injection, purge 1 (N2), reactant exposure (O2 plasma), and purge 2 (N2). (source)
There were also presentations by Applied Materials (AMAT) and although less details were presented, I noted a remark from Shimon Levi that the AMAT SAQP process was also a spacer-on-spacer process. To reduce profile variation, Regina Freed told that AMAT also implemented an additional hard mandrel etch. So their process might be similar to that of TEL.
One could also wonder what will happen to SAxP once EUV lithography will be implemented. A presentation by Frederic Lazzarino of imec was quite insightful in this respect. For imec’s 3nm technology node, he compared three approaches:
- 193 nm immersion lithography with SAQP
- EUV lithography with SADP
- 193 nm immersion lithography with SAOP (O = octuple)
He discussed that the EUV approach would lead to serious concerns with respect to line-edge-roughness and line-width-roughness (LER and LWR) whereas the SAOP approach would probably be problematic in terms of pitch walk. The best approach would probably be 193 nm immersion lithography with SAQP but with additional photoresist trimming which can be done in the PEALD reactor as he demonstrated. So for this application, SAQP might still be able to push out the introduction of EUV.
To conclude this blog: what else fascinating did I learn during the SPIE lithography 2017 conference? Well, it became clear to me that pellicles for EUV are a very hot topic. A pellicle is an ultrathin, transparent membrane that covers the photomask and prevents particles and contaminates from falling on the mask. ASML is pushed hard to come up with a good solution for their EUV tool which seems to be far from trivial. As stated by Intel: “a high-transmission EUV pellicle with a survivability at high power is a missing piece”. They mentioned that other approaches (than the poly-Si pellicle by ASML or the SiNx pellicle by IBM) will eventually be needed for 350 W source power. Ivan Pollentier from imec presented an interesting approach for 250 W source power. They used freestanding carbon nanotubes (CNTs) to form a pellicle. They addressed the mechanical, thermal and chemical stability. With respect to the latter, the etching of the CNTs by atomic hydrogen in the scanner is a major concern but they were able to solve this by coating the CNTs with a thin film. This leads to a loss of transmission but it makes the pellicle chemical stable. From the acknowledgment I learned that the preparation method of this film was ALD (likely Ru?). Well, what else?
Leave a Reply