We just published a perspective article entitled “From the bottom-up: towards area-selective atomic layer deposition with high selectivity”.1 This perspective describes the current status of the field of area-selective atomic layer deposition (ALD), and also includes my vision on how we can improve the selectivity. It is published in Chemistry of Materials as part of the “Up-and-coming” series for early career scientists in material science,2 which also included some earlier contributions on ALD.3,4 Especially in the past few years, the topic of making ALD processes selective has become a very active research topic in both academia and industry, and there has been a clear shift in the motivation why we need area-selective deposition.
Our perspective on area-selective ALD is available open access from https://pubs.acs.org/doi/abs/10.1021/acs.chemmater.8b03454
From ALD-enabled nanopatterning to self-aligned fabrication
Five years ago, at the end of my PhD project, I wrote a review paper entitled “The use of atomic layer deposition in advanced nanopatterning”.5 Back then, our focus was on what we described as ALD-enabled nanopatterning. For example, we worked on patterning electrical contacts on emerging nanomaterials such as carbon nanotubes and graphene.6,7 The motivation for this type of work – nicely illustrated in the movie below – was that these sensitive materials are not compatible with etching or the use of resist films, and it is therefore needed to perform the patterning in a purely bottom-up fashion.
Area-selective ALD – here in the configuration of direct-write ALD – can be used to pattern electrical contacts on sensitive nanomaterials such as carbon nanotubes or graphene.6,7
This review paper was published just before the recent surge of interest in area-selective deposition, caused by the imminent need for self-aligned fabrication in semiconductor processing. There were some signs that area-selective ALD was being considered for self-aligned fabrication, and I remember that we added a section on this topic just before submitting it for publication. When you read that section, it is clear that there were only a few examples of the use of area-selective ALD in self-aligned fabrication schemes at that stage.
In the past few years, self-aligned fabrication has become the main motivation to develop area-selective ALD processes. This is of course connected to the fact that for sub-5 nm critical dimensions, alignment is becoming a major bottleneck that limits the downscaling of nanoelectronics. The figure below shows an example of an application that is currently being developed in the semiconductor industry. By implementing a dielectric-on-dielectric area-selective ALD step, more reliable interconnects can be fabricated.
Schematic illustration of how area-selective ALD can enable the fabrication of fully self-aligned vias. When patterning vias with tight spacing, in practice there is often an edge placement error (EPE) that can lead to an increased RC delay or even shunting of the device. A solution is to use an area-selective ALD process for dielectric-on-dielectric deposition (with Cu or Co as the non-growth area). Even if the via is patterned at exactly the same location, the additional spacing provided by the barrier reduces the RC delay and makes the device more reliable.
The main challenge: area-selective ALD with high selectivity
The aim for self-aligned fabrication means that we do not have to focus on patterning itself, but instead we can consider the situation that several different materials are present in a device structure, and that the deposition needs to occur on only one of these materials. One of the main challenges for area-selective ALD is to achieve a sufficiently high selectivity (i.e. a measure for the amount of material that is deposited on the growth and non-growth areas), which is the topic of the perspective. So far, for all the approaches that have been developed for area-selective ALD, the problem is that the selectivity is eventually lost, and growth is also obtained on surfaces where no deposition is desired.
We asked ourselves the question what the target selectivity should be. For applications in catalysis, some of the existing area-selective ALD processes might be good enough. However, the applications in nanoelectronics are much more demanding. In a way, one can argue that for most nanoelectronics applications, we only need a film of a few nanometers thick, which appears within reach for some area-selective ALD approaches. However, in practice, the growth will also initiate on defects and impurities on those surfaces on which no deposition is desired, deteriorating the device performance. As we discuss in the perspective, applications in nanoelectronics might require a selectivity as high as 0.99999999, a far cry from what has been demonstrated.
Towards high selectivity
Conventionally, most area-selective ALD approaches rely on surface functionalization prior to the deposition. In my vision, we need to implement various correction steps to enhance the selectivity. For example, surface functionalization can be repeated during the deposition,8,9 to correct for the fact that the ALD chemistry can deteriorate the blocking ability of molecules on the non-growth area. Repetition of surface functionalization in an ABC-type ALD (i.e. three-step) offers additional merits such as the ability to use ozone or plasmas as co-reactant.9 Moreover, etching steps can be included to remove unwanted deposition from the non-growth area.10,11 This requires the development of supercycle recipes in which deposition and etching cycles are combined.
The implementation of these corrections steps results in the development of advanced ALD cycles, which includes ABC- and ABCD-type cycle and supercycle recipes. In our own work, we focus on vapor-phase correction steps, as this leads to approaches that are very compatible with semiconductor process flows. I believe we will eventually need combinations of various correction steps to achieve the target selectivity values. For instance, the figure shown below illustrates an ALD cycle in which ABC-type ALD cycles (involving repetition of surface functionalization) are combined with etching steps in a supercycle recipe.
Advanced ALD cycle in which surface functionalization (in ABC-type cycles) and selective etching (e.g. ALE) correction steps are combined in a supercycle recipe.
The implementation of correction steps involving selective etching will also require the development of atomic layer etching (ALE) processes. Luckily, we can benefit from the increased research activity in the ALE field. There some interesting parallels that can be drawn between how to achieve selectivity in area-selective ALD and in ALE. For example, deposition of fluorocarbon is employed in ALE of SiO2 to achieve selectivity.12 The two fields are approaching each other, and I expect that we will see many more examples of combinations of area-selective ALD and ALE in the next few years. It makes me wonder whether in another five years we will still be talking about area-selective ALD and ALE separately, or as selective atomic-scale processing instead.
(1) Mackus, A. J. M.; Merkx, M. J. M.; Kessels, W. M. M. From the Bottom-Up: Toward Area-Selective Atomic Layer Deposition with High Selectivity. Chem. Mater. ASAP, https://pubs.acs.org/doi/abs/10.1021/acs.chemmater.8b03454
(2) Buriak, J. M. Up-and-Coming Perspectives: Share the Excitement of Top Early Career Researchers in Materials Chemistry. Chem. Mater. 2016, 28 (12), 4083–4084.
(3) Pedersen, H. Time as the Fourth Dimension: Opening up New Possibilities in Chemical Vapor Deposition. Chem. Mater. 2016, 28 (3), 691–699.
(4) Kim, H. G.; Lee, H. B. R. Atomic Layer Deposition on 2D Materials. Chem. Mater. 2017, 29 (9), 3809–3826.
(5) Mackus, A. J. M.; Bol, A. A.; Kessels, W. M. M. The Use of Atomic Layer Deposition in Advanced Nanopatterning. Nanoscale 2014, 6, 10941–10960.
(6) Thissen, N. F. W.; Vervuurt, R. H. J.; Mackus, A. J. M.; Mulders, J. J. L.; Weber, J. W.; Kessels, W. M. M.; Bol, A. A. Graphene Devices with Bottom-up Contacts by Area-Selective Atomic Layer Deposition. 2D Mater. 2017, 4, 025046.
(7) Mackus, A. J. M.; Thissen, N. F. W.; Mulders, J. J. L.; Trompenaars, P. H. F.; Chen, Z.; Kessels, W. M. M.; Bol. Resist-Free Fabricated Carbon Nanotube Field-Effect Transistors with High-Quality Atomic-Layer-Deposited Platinum Contacts. Appl. Phys. Lett. 2017, 110, 013101.
(8) Hashemi, F. S. M.; Bent, S. F. Sequential Regeneration of Self-Assembled Monolayers for Highly Selective Atomic Layer Deposition. Adv. Mater. Interfaces 2016, 3, 1600464.
(9) Mameli, A.; Merkx, M. J. M.; Karasulu, B.; Roozeboom, F.; Kessels, W. M. M.; Mackus, A. J. M. Area-Selective Atomic Layer Deposition of SiO2 Using Acetylacetone as a Chemoselective Inhibitor in an ABC-Type Cycle. ACS Nano 2017, 11, 9303–9311.
(10) Hashemi, F. S. M.; Prasittichai, C.; Bent, S. F. Self-Correcting Process for High Quality Patterning by Atomic Layer Deposition. ACS Nano 2015, 9, 8710–8717.
(11) Vallat, R.; Gassilloud, R.; Eychenne, B.; Vallée, C. Selective Deposition of Ta2O5 by Adding Plasma Etching Super-Cycles in Plasma Enhanced Atomic Layer Deposition Steps. J. Vac. Sci. Technol. A 2017, 35 (1), 01B104-1-01B104-7.
(12) Metzler, D.; Bruce, R. L.; Engelmann, S.; Joseph, E. A. Fluorocarbon Assisted Atomic Layer Etching of SiO2 Using Cyclic Ar/C4F8 Plasma. J. Vac. Sci. Technol. A 2014, 32 (2), 020603.