Please cite asM.J.M. Merkx, A.J.M. Mackus, Area-selective ALD of diffusion barriers for via optimization – There is plenty of room at the bottom. 2022, 7. AtomicLimits.
This week the 6th area-selective deposition (ASD) workshop will be held in San Francisco, California. During this workshop, we will present our latest work on area-selective ALD of TaN.1 In this blog post, we elaborate on a potential application of TaN ASD in the semiconductor industry. This post is the third part of a series on area-selective deposition (ASD) applications that we have evaluated with the focus on the back-end-of-line of semiconductor device fabrication. Previous posts have highlighted the Fully Self-Aligned Via (FSAV) structure and selective metal capping for improved electromigration resistance. Whereas the previous posts explored applications for dielectric-on-dielectric (DoD) and metal-on-metal (MoM) ASD, this post highlights a potential application for metal-on-dielectric (MoD) ASD.
Challenges in scaling down the back-end-of-line
The main purpose of the back-end-of-line (BEOL) is to scale up from the nanoscale devices in the front-end-of-line (FEOL) to the external wiring that connects the IC to the wiring outside of the chip. The BEOL of an integrated circuit (IC) largely consists of many patterned layers of metal wiring (typically Cu) and so-called interlayer dielectric (ILD, typically carbon-doped oxide). The Cu wires serve to connect the devices in the FEOL, while the ILD separates the individual metal wires such that shorts are prevented, see Figure 1. The metal wiring is enveloped with a diffusion barrier to prevent Cu diffusion into the ILD. In addition, a multilayered dielectric barrier is deposited in between each metal level, which acts as: etch stop during fabrication, passivation against electromigration, and diffusion barrier. State-of-the-art ICs contain a stack of many patterned layers in the BEOL. Each of these layers is typically referred to as Mx (e.g. M1, M2), starting with M0 closest to the FEOL. Because of downscaling in the FEOL, downscaling of the BEOL is also required in concert with a larger number of metal layers, i.e., the wiring is more complex/dense and it takes more steps to scale up to the dimensions of the outside wiring. As a result, BEOL architectures have become increasingly complex.
The increasing demand for device downscaling is causing issues related to the resistance of Cu interconnects, especially for the metal lines and vias near the FEOL.2,3 Aside from an overall decrease in Cu interconnect cross-sectional area, one of the main challenges is that proportional downscaling of the diffusion barrier with the interconnect is typically not possible as it compromises its ability to prevent Cu diffusion into the surrounding ILD.3 As a result, interconnect downscaling has caused the diffusion barrier to take up an increasing portion of the interconnect volume with respect to the Cu, see Figure 2. This relative decrease in Cu volume leads to an exponential increase in Cu interconnect resistance for scaling to smaller dimensions.4,5 In addition, the reduced Cu volume also increases the susceptibility of the interconnect structure for defects formed by electromigration.
Using ALD for diffusion barrier deposition
Conventional interconnect technology relies on a physical vapor deposition (PVD) of a diffusion barrier layer (typically a metal nitride e.g., TaN) during BEOL fabrication.6 However, PVD has a limited uniformity on structures with 3D topographies (i.e. conformality).7,8 Therefore, to ensure the minimum barrier thickness is achieved in the entire structure, a relatively thick layer needs to be deposited,9 as illustrated in Figure 3a. Instead of PVD, atomic layer deposition (ALD) can be used to deposit a more conformal barrier layer.7,10,11 There are several benefits to using ALD to deposit the barrier layer. ALD is mostly known for its ability to deposit ultrathin films with excellent uniformity on structures with 3D topographies. For this application, the uniformity of ALD allows for lowering the nominal thickness of the barrier layer (i.e., there is no need to account for the non-uniformity), which leaves more room for filling up the trench with conductive Cu, as shown in Figure 3b. The use of ALD for deposition of TaN barrier layers has been explored extensively in the literature, especially in the early 2000s.12,13 The interest in employing ALD for this application faded when it turned out that PVD could still deliver the desired performance in terms of barrier properties and uniformity for a few more technology nodes, and therefore there was no need to introduce new methods and tools for ALD diffusion barriers into the process flow. However, it is expected that the ability of ALD to deposit films with an unparalleled uniformity on topographical structures will become essential at the smaller dimensions of devices in future technology nodes.
The bottomless barrier
A more important issue regarding diffusion barriers is that the barrier is deposited over the entire 3D structure. As a result, it also covers the metal from the previous layer at the bottom of the trench. Consequently, each metal level is separated by a barrier layer in the final structure (Figure 2), which adds a series resistance to the overall interconnect resistance. As a result, the barrier is required to be highly conductive. In addition, the diffusion barrier at the bottom, covering the underlying metal, makes a selective via filling of the metal interconnect impossible, as discussed in our previous blog post. The bottom part of the diffusion barrier serves no purpose in terms of preventing Cu diffusion since it separates two Cu regions and is therefore not desired. Preferably, the diffusion barrier only covers the dielectric sidewalls of the interconnect structure, which is referred to as a bottomless barrier, see Figure 4. Having no diffusion barrier at the bottom of the via structure is beneficial for the overall interconnect resistance, thereby improving the RC-delay. In the bottomless barrier structure, the conductivity of the diffusion barrier should have no to almost no impact on the overall via resistance depending on the fraction of via volume that the barriers on the sidewalls occupy. As a result, the requirements of the diffusion barrier in terms of its conductivity are likely much more relaxed as compared to a conformal barrier. This provides the opportunity to optimize the barrier material for preventing Cu diffusion without having to worry too much about the conductivity of the film potentially even allowing for dielectric diffusion barriers. This relaxation in the electrical requirements of the diffusion barrier should allow for even thinner barriers covering the ILD.
There are two general strategies to achieving a bottomless barrier structure: (i) selective etching of material at the bottom of the trench or (ii) selective deposition of the diffusion barrier on the dielectric surfaces. Typically, etching of material at the bottom of a trench is achieved using an anisotropic etching process,14,15 i.e., using directional ions to only etch on horizontal planes. Two patents by Intel (2008 and 2012) 14,15 describe strategies to obtaining a bottomless barrier/liner structure by selectively etching the material at the bottom. They mention the use of a sputter etch14 as means to anisotropically and selectively etch the barrier at the bottom. However, using an anisotropic etch to fabricate a bottomless barrier is not trivial because interconnect structures typically also have horizontally-oriented ILD surfaces that also need to be covered with the diffusion barrier (see Figure 3).
The bottomless barrier structure can also be obtained by ASD of the barrier on the ILD and not on the metal at the bottom of the trench, as shown in Figure 4. Area-selective ALD is ideal for this application as it combines the bottomless barrier with having a thin conformal barrier covering the ILD. Patents by ASM (2005)16 and Novellus systems (2003; acquired by Lam Research Corp. in 2011)17 mention obtaining a bottomless barrier structure using ASD, either through surface activation of the dielectric16 or inherently selective deposition.17 A recent patent by IBM (2021)18 also mentions using ASD to obtain a bottomless barrier structure. Although it is not specifically mentioned which method they aim to use to obtain selective deposition, they also refer to area-selective ALD literature using small molecule inhibitors (SMIs) to passivate the non-growth area.18
Selective via filling and bottomless barrier
As mentioned above, selective via filling is not viable if a conformal barrier or liner material is deposited before metallization. However, the bottomless barrier leaves the underlying metal from the previous layer exposed for the subsequent via filling process. Therefore, in case of a bottomless barrier, via filling could be achieved directly on the exposed metal through e.g., electroless deposition or area-selective CVD, see Figure 5. As a result, the bottomless barrier and selective metal-on-metal deposition for via filling could be a very powerful combination for the semiconductor industry to solve some of the current issues in the BEOL associated with downscaling. Potentially, the advantages of combining the bottomless barrier structure with selective via filling could enable the adoption of both of these processes by industry simultaneously.
Area-selective ALD of nitrides
Typically, transition metal nitrides are employed as diffusion barriers.19–22 Therefore, the bottomless barrier application requires deposition of a metal nitride on the ILD growth area (e.g., SiO2/ carbon-doped oxide) while deposition on the metal non-growth area (e.g., Cu, Co, Ru, or W) should be prevented. Currently, the target thickness for diffusion barriers in state-of-the-art device structures is ~3 nm,2 which is well suited for area-selective ALD as it falls within the typical selectivity windows of recently developed area-selective ALD processes.23–27 Effective TaN barriers to prevent Cu diffusion have even been reported with film thickness down to 0.6 nm.22 An advantage of this ASD application is that any reduction in the deposited barrier material on the metal, with respect to a non-selective deposition, will improve the conductivity of the interconnect structure. Therefore, although no deposition on the metal at the bottom is of course preferred, loss of selectivity should not directly lead to device malfunction for this application. In other words, the bottomless barrier application has a higher tolerance for loss of selectivity as compared to other applications of ASD currently in focus, making adoption into industry easier.
What is currently possible based on the currently developed area-selective ALD processes? Recently, Lionti et al. from IBM reported on an area-selective TaN ALD process using cross-linked SAMs to deposit up to 3.8 nm TaN selectively on SiN or mesoporous SiCOH without detectable deposition on Cu or W.25 In addition, TEL has reported to have an area-selective TaN ALD process using SAMs for the bottomless barrier application.28 In our recent work, we achieved area-selective ALD of TiN24 and TaN1 (to be presented at ASD 2022) on oxide material (SiO2, Al2O3) in the presence of a metal (Co, Ru) using aniline as SMI. Using these process, 3 nm of TiN or TaN can be deposited on an oxide with a selectivity of ~0.9 or better with respect to a Ru or Co non-growth area. The TiN process was demonstrated to also yield good selectivity on patterned substrates at nanoscale dimensions.
Although the earliest patents on bottomless barrier structures date back to 20 years ago, only recently the reports on metal nitride ASD processes suitable for this application is starting to pick up. The semiconductor industry seems eager to adopt the bottomless barrier in their interconnect structures. The bottomless barrier application could therefore play a key role in interconnect scaling and in further maturing the field of area-selective ALD.
We would like to acknowledge Rik Lengers and Jun Li for the excellent help with the literature study on (bottomless) diffusion barriers
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(2) Brain, R. Interconnect Scaling: Challenges and Opportunities. In 2016 IEEE International Electron Devices Meeting (IEDM); IEEE, 2016; pp 9.3.1-9.3.4. https://doi.org/10.1109/IEDM.2016.7838381.
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